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I have finally completed the design and documentation of EDUC-8L, which adds a link bit to EDUC-8 along with 16 new instructions. The modifications add a total of 12 additional chips to EDUC-8, or 0.75 chips per instruction! You can download my paper on EDUC-8L using the link below. The paper includes an updated Program Encoding Guide as well as five pages of schematics.

http://www.sworld.com.au/steven/educ-8/educ-8l.pdf

Next up is adding interrupts to EDUC-8. When writing to the input device (ID) or output device (OD) field, the data in the AC before writing will be XYZ, in 737 format. X selects one of eight EDUC-8ME units. Z selects one of the eight ID or OD ports. Y is normally 0. Each unit will have two 74259 addressable latches that contains the interrupt enable for each ID and OD port. If Y = 2, then the interrupt enable for port Z is disabled. If Y = 3 the interrupt enable for port Z is enabled. If Y = 1, then all the interrupt enables are disabled.

Similar to PDP-8, the additional instructions are

605 IOF Interrupts Off
615 ION Interrupts On (after one additional instruction)
625 SON Skip if Interrupt System On
635 SRQ Skip on Interrupt Request

There are no special instructions to get all the registers, like with PDP-8, since AC does not have enough space to do that. The AC, L, IF, DF, ID and OD will need to be saved using existing instructions. On an interrupt (which occurs if a device flag goes high and its interrupt enable latch is on), the IF will be loaded into the EDUC-8ME parallel to serial converter, after which the IF will be cleared.

The PC will be loaded into address 010 (to avoid using the eight page zero values) with instructions starting at 011. After saving AC and L, the first read from EDUC-8ME must be of the IF, as the interrupt state machine will disable loading the parallel to serial converter to prevent the IFR instruction reading the actual all zero IF. It will instead read the IF before the interrupt. After the first read from EDUC-8ME, the DF, ID and OD can then be normally read and saved

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I've made another update to EDUC-8ME. I found there was a bug in the design due to the use of the OPR+IOT signal in E8ME/B. This signal can be high during EXAMINE and DEPOSIT and will thus cause an incorrect field to be addressed since the 2-bit MEA address could be non-zero. This has been corrected, along with many other minor improvements. I've also managed to delete one chip in E8ME/D! You can download the updated PDF from the link below.

http://www.sworld.com.au/steven/educ-8/educ-8me.pdf

I've also updated the design of EDUC-8L which adds the link bit and its associated instructions. I've also added other instructions that were used on the PDP-8 as well as one new instruction that wasn't included! Here's the list of the 16 new instructions.

715 DAC (decrement accumulator)
712 OSR (OR switch register with accumulator)
706 BSW (byte swap, exchange AC[7:4] with AC[3:0])
703 RLL (rotate link left through AC register)
713 CLL (clear link)
707 CML (complement link)
717 STL (set link)
731 RTL (rotate link twice left through AC register)
725 RTR (rotate link twice right through AC register)
732 SNA (skip on nonzero accumulator)
726 SPA (skip on positive accumulator)
736 SNA.SPA (skip on non-zero and positive accumulator)
723 RLR (rotate link right through AC register)
733 SZL (skip on zero link)
727 SNL (skip on nonzero link)
737 SKP (skip)

I'm still working on the documentation for EDUC-8L and will send that to the group once it is finished. Once that is done, I will be doing another update of EDUC-8ME that will include the option of adding interrupts! All these updates will make EDUC-8 into a quite powerful little machine.

I've made a fairly large update to EDUC-8ME, a memory and I/O port expansion for EDUC-8. I have moved the unit selection and address decoding logic from E8ME/D to E8ME/I. This means that E8ME/D is only required in the first EDUC-8ME unit, reducing complexity if more than one unit is used and reducing the load on the switch register. I've also updated the E8ME/M boards to allow the option of using 2102 or 2125 1Kx1, 2147 4Kx1 or 2167 16Kx1 SRAMs. There are also many other minor updates. You can download the updated paper and schematics from the link below.

http://www.sworld.com.au/steven/educ-8/educ-8me.pdf

Next up is documenting the schematics for EDUC-8L, which adds a link bit to EDUC-8.

Repairing the original machine rn. Will document in a new thread when I figure out how

Quote from: monsonite on May 02, 2024, 03:19 AMHi All, as a newcomer to this project could you please point me to somewhere that has these resources.

Is there a central repo on Github?

TIA


Ken

The Resources section of this site has some. Just trying to get all the info in...
https://educ8.taswegian.com/index.php?board=4.0

The Github repo is also listed in the Links section.
https://educ8.taswegian.com/index.php?board=2.0

Hi All, as a newcomer to this project could you please point me to somewhere that has these resources.

Is there a central repo on Github?

TIA


Ken